In the frames of Goepel's GATE™ program Testonica Lab develops and delivers processor' models for Scandinavian customers. models enable emulation-based (processor-controlled) test of PCBs. VarioTAP® technology utilizes debug capabilites of on-board MPUs and MCUs for emulation-based (processor-controlled) Flash ISP and testing of peripherals (memories, I/O connectors). VarioTAP® supports many kinds of proprietary debug architectures of different chip vendors including ICs with non-JTAG debug interface. The VarioTAP® models are fully supported by JTAG development environment – System CASCON.
Processor support for the following devices is available:
For questions regarding the support of devices that are not listed above, please contact our team variotap[at]testonica.com